1. Field of the Invention
The present invention relates to systems and methods for power supply regulation for semiconductor devices. More particularly, the invention relates to voltage regulation using passive semiconductor devices.
2. Description of Related Art
Current system on a chip (SOC) devices are being pushed towards increased integration of functionality and optimization of power/performance. Because of the increased functionality integration requirements, multiple IP blocks from multiple sources (an IP block is a reusable unit of logic, cell, or chip layout design that sometimes comes from a different single party or source) are increasingly being added to SOC devices. Each individual IP block may have its own unique power supply requirements and power delivery challenges. For example, one IP block may operate using a supply voltage that is different than other supply voltages currently available. The different supply voltage may only vary slightly from the current supply voltages (e.g., even only about 100 mV difference) but the different supply voltage may draw significant amounts of current. Because of the high current draw and the importance of energy efficiency, a simple LDO (low-dropout) linear regulator off the higher of the two supply voltages may not be a satisfactory solution for low-power designs. The combination of the drive for power efficiency and the existence of many supply voltage requirements on the SOC device may produce a fairly complex design for the connection between the SOC device and a power management unit (PMU).
The use of individual IP blocks may also provide multiple different complex analog functions in the SOC device. Some of these analog functions may benefit from operation at higher voltage supplies. Supplying the higher voltages across the device to provide the improvements in analog performance in one particular sub-portion may, however, create power inefficiencies in operation of the overall device. Thus, providing the higher supply voltages directly for analog functions such as amplifiers and current sources (e.g., supplying the higher supply voltages to the analog functions separately from other supply voltages) may allow for stacking of devices in cascode, Wilson, and/or other configurations that may improve analog performance in these critical areas.
Another issue with increasingly complex SOC devices is that there are significant resistances across the devices as the number of power consuming structures (e.g., transistors) in the device increases. To maintain the highest delivered performance for the last power consuming structure (e.g., the power consuming structure “furthest” from the PMU or the last power consuming structure experiencing the largest voltage drop), the supply voltage across the SOC device needs to be as high as possible. Raising the supply voltage, however, is constrained by the highest compliance voltage that can be tolerated by the first power consuming structure closest to the PMU. Because the supply voltage upper limit is set by the tolerance of the closest power consuming structures, the IR drop (voltage drop across the device) at the last power consuming structure becomes an uncompensated loss, which can limit performance of an SOC device. This voltage drop is becoming a more significant issue as it becomes a larger percentage of the supply voltage due to the reduction in power supply voltages. This reduction itself is driven by a desire to reduce power consumption (e.g., to reduce battery consumption and increase battery life). In addition, the reduction in performance may be exacerbated by the fact that device threshold voltage (VT) is not scaling. Thus, for example, a 10% reduction in power supply voltage may result in a 20%-30% slowdown in gate speed (e.g., transistor speed), further exacerbating the effect of I*R drop on SOC performance.
Another issue with providing power supplies at lower voltages is the dramatically increased current required when selected sub-blocks of the SOC device transition into a highly active mode. During the highly active mode of the selected sub-blocks, other sub-blocks (e.g., different CPUs or GPUs) may be idle or consuming substantially lower current. These idle sub-blocks would ideally be maintained on a different power supply rail in order to sufficiently isolate power delivery and provide separate DVFS (dynamic voltage frequency scaling) settings and power-down functions. Separating the power supply rails means that there are no shared resources on SOC power delivery between the selected sub-blocks and the idle sub-blocks. Such resources could include bumps or balls on the package as well as routing and components on the printed circuit board. Placing such constraints on the SOC device may require significant design complexity in the package in order to provide an expanding group of low inductance power delivery networks.